1. Field of the Invention
The present invention relates to a solid-state image pickup device typified by CMOS image sensor, a method of driving the same, and camera system using the image pickup device.
2. Description of Related Art
A CMOS image sensor has recently been paid attention as a solid-state image sensor to be substituted for a charge-coupled device (CCD).
This is because a CMOS image sensor overcomes various issues that a system becomes very complicated, including a necessity of dedicated processes for manufacture of CCD pixels, a necessity of a plurality of power supply voltages for operation, and a necessity of combining a plurality of peripheral ICs for operation.
A CMOS image sensor allows the manufacturing processes similar to those for a general CMOS integrated circuit. In addition, the CMOS image sensor may be driven by a single power source, and may be implemented in the same chip as that of analog circuits and logical circuits using CMOS processes. Thus, the CMOS image sensor has a plurality of considerable merits such as reduction in the number of peripheral ICs.
The main trend of an output circuit in a CMOS image sensor is a one-channel output by using an FD amplifier with a floating diffusion (FD) layer.
In contrast, a CMOS image sensor has an FD amplifier at each pixel, and the main trend of the output method is a column-parallel output type that each row in a pixel array is selected and the selected pixel signals in the row are read out to column directions at the same time.
This is because parallel processing is advantageous since the FD amplifiers disposed within the pixels are difficult to obtain a sufficient driving ability and therefore a data rate is required to be lowered.
A large variety of signal output circuits have been proposed for a column-parallel output type CMOS image sensor. One of most advanced types is that an analog-to-digital converter (hereinafter abbreviated as “ADC”) is provided for each column and a pixel signal is outputted as a digital signal.
A CMOS image sensor mounting column-parallel type ADC is disclosed, for example, in “An Integrated 800×600 CMOS Image System”, by W. Yang et. al., ISSCC Digest of Technical Papers, pp. 304 and 305, February, 1999, and Japanese Unexamined Patent Application Publications Nos. 2005-303648 and 2005-323331.
FIG. 1 is a block diagram showing a configuration example of solid-state image pickup device (CMOS image sensor) with a column-parallel ADC.
The solid-state image pickup device 1 includes a pixel array unit 2 as an imaging unit, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, a digital-analog converter unit (hereinafter abbreviated to a DAC (digital-to-analog converter)) 7, and a data output circuit 8 including a sense amplifier circuit (S/A).
The pixel array unit 2 is composed of unit pixels 2-1, each including a photodiode and an intra-pixel amplifier, disposed in a matrix.
The solid-state image pickup device 1 includes a control circuit for sequentially reading out pixel signals of the pixel array unit 2. The control circuit includes a timing control circuit 5 for generating internal clocks, a row scanning circuit 3 for controlling row addressing and row scanning, and a column scanning circuit 4 for controlling column addressing and column scanning.
The ADC group 6 includes column-parallel ADC blocks 6-4 each having an ADC 6A disposed for each of column lines V0, V1, . . . of columns of the pixel array unit. The ADC blocks are composed of: (n+1) comparators (REF) 6-1 disposed for the columns of the pixel array unit; asynchronous up/down-counters (hereinafter called counters) 6-2; memories (latches) 603, and switched 6-4. The comparator (REF) 6-1 compares a ramp waveform RAMP obtained by stepwise changing a reference voltage generated by DAC 7 with each of analog signals supplied from each of row lines H0, H1, . . . via column lines V0, V1 . . . . The counter 6-2 counts up (or down) upon reception of an output of the comparator 6-1 and a clock CK. The memory 6-3 holds a count value of the counter 6-2. The switch 6-4 selectively connects either an output of the counter 6-2 or the memory 6-3 in response to a signal SW.
An output of each memory 6-3 is connected to 2n data transfer lines 9 each having a 2-bit width. A data output circuit 8 including 2n sense circuits and 2n subtractor circuits is disposed for the 2n data transfer lines 9.
The counter 6-2 having a holding circuit function is in an up-count (or down-count) state at the initial stage to perform reset count. When the counter 6-2 performs reset count to invert an output COMPOUTi of the corresponding comparator 6-1, the counter 6-2 stops the up-count operation and holds the count value in the memory 6-3.
In this case, the initial value of the counter 6-2 is assumed to have an arbitrary value of gradation of AD conversion, e.g., a value of “0”. During this reset count period, reset components ΔV of the unit pixel 111 are read out.
Thereafter, the counter 6-2 enters a down-count state, performs data count corresponding to an incident light amount. When the output COMPOUTi of the corresponding comparator 6-1 is inverted, a count value corresponding to a comparison period is held in the memory 6-3.
The count values held in the memories 6-3 are scanned by the column scanning circuit 4, and inputted to the output circuit 8 via the data transfer lines 9.
Here, the operation of the solid-state image pickup device (CMOS image sensor) 1 will be described.
After a first readout operation from the unit pixels 2-1 at an arbitrary row Hx to the column lines V0, V1, . . . is stabilized, DAC 7 supplies the comparators 6-1 with the ramp waveform RAMP obtained by changing stepwise the reference voltage depending on time, and each comparator 6-1 compares RAMP with a voltage at the corresponding column line Vx.
In parallel with stepwise input of the ramp waveform RAMP, the counter 6-2 performs a first count operation.
In this case, when RAMP and a voltage at the column line Vx becomes equal, an output of the comparator 6-1 is inverted, so that the count operation of the counter 6-2 stops and a count value corresponding to the comparison period is held in the memory 6-3.
During the first readout operation, the reset components ΔV of the unit pixel 2-1 are read out. The reset components ΔV contain noises varying in each unit pixel 2-1 as an offset.
However, a variation in the reset components ΔV is generally small, and the reset level is common for all pixels. As a result, an output at each column line Vx has generally a known value.
Accordingly, during the first reset components ΔV readout operation, the comparison period can be shortened by adjusting a ramp waveform (RAMP) voltage. In this case, for example, comparing ΔV is performed during a count period of 7 bits (128 clocks).
The second readout operation performs an operation similar to the first readout operation, by reading out signal components corresponding to an incident light amount of each unit pixel 2-1 in addition to the reset components ΔV.
Namely, after the second operation of reading out from the unit pixels 2-1 at the arbitrary row Hx to the column lines V0, V1, . . . is stabilized, DAC 7 supplies the comparators 6-1 with the ramp waveform RAMP obtained by changing stepwise the reference voltage with time, and each comparator 6-1 compares RAMP with a voltage at the corresponding column line Vx.
In parallel with stepwise input of the ramp waveform RAMP, the counter 6-2 performs a second count operation.
In this case, when RAMP and a voltage at the column line Vx becomes equal, an output of the comparator 6-1 is inverted and the count value corresponding to the comparison period is held in the memory 6-3 at the same time.
In this case, the first count value and second count value are held in the memory 6-3 at different positions.
After the completion of the above-described AD conversion, the column scanning circuit 4 transfers the first and second digital signals of n-bit held in the memories 603 via the 2n data transfer lines, the data output circuit 8 detects the digital signals, and the subtractor circuits sequentially perform (second signals)-(first signals) and the results are outputted to the external. Thereafter, a similar operation is sequentially repeated for each row to generate a two-dimensional image.
The above operation is performed in one horizontal unit period (1H).
During 1H, the first readout operation from the unit pixels 2-1 at an arbitrary row Hx to the column lines V0, V1, . . . is represented by a P-phase readout PR, the first comparison at the comparator 6-1 is represented by a P-phase comparison PC, the second readout operation is represented by a D-phase readout DR, the second comparison at the comparator 6-1 is represented by a D-phase comparison DC, and a post process after D-phase processing is represented by a post D-phase process DAP, each operation being continuously performed.
The timing control circuit 5 performs timing control of the P-phase readout PR, P-phase comparison PC, D-phase readout DR, D-phase comparison DC, and post D-phase process DAP.
As shown in FIG. 2, in the timing control circuit 5, two circuits each having a 12-bit register 5-1, a 12-bit counter 5-2, and a comparator 5-3 are used fundamentally in order to set a rising and falling of a timing signal TMG.